In the fabrication of integrated circuits using metal oxide semiconductor (MOS) techniques, gate oxide layers are becoming increasingly thinner in order to achieve further increases in transistor performance. For a given set of terminal voltages, the drain current of an MOS transistor is inversely proportional to the thickness of the gate oxide layer. A thin gate transistor may have a 15 nm gate oxide.
A concern in the operation and handling of circuits having thin gate transistors is the susceptibility of the circuits to damage caused by electrostatic discharge (ESD). The dielectric breakdown strength of silicon dioxide is approximately 8.times.10.sup.6 V/cm, so that a 15 nm gate oxide will be unable to withstand a voltage exceeding 12 V. However, an ESD pulse may have a peak of several thousand volts. A primary source of ESD pulses is human handling of an integrated circuit package having input/output pins or pads.
Circuits for providing ESD protection are known. FIG. 1 is a prior art ESD protection circuit. A signal is applied at an input pad or pin 10. A first transistor 12 and a second transistor 14 are employed to discharge high voltage pulses. A negative-going pulse generated by an ESD strike is discharged via the first transistor 12. The gate 16 of the first transistor is tied to V.sub.cc. A negative-going ESD pulse will turn on the second transistor 14, which has a source 18 that is tied to ground. The first and second transistors will discharge most of the ESD pulse by establishing a path to either V.sub.cc or ground, with much of the remainder of the charge being discharged via a third transistor 20 by means of drain voltage punch through. Bipolar turn-on of parasitic bipolar transistors of the first, second and third transistors accounts for additional pulse discharge.
The circuit of FIG. 1 has a number of limitations. The first and second transistors 12 and 14 are typically metal field effect transistors having a high turn-on voltage, e.g., 15-20 V, and having long channel lengths. Consequently, the two transistors carry some inherent inefficiency in discharging an ESD pulse. Charge from an ESD pulse which is not sufficiently discharged may pass to internal circuitry 22 which is to be protected. The charge may damage gates of transistors of the circuitry 22.
Another limitation of the circuit is that while the third transistor 20 is a thin gate transistor, its connection within the circuit renders the third transistor susceptible to gate-aided junction breakdown. If the voltage across the transistor exceeds the breakdown voltage of the device, damage to the transistor may result in permanent shorting of the input signal to ground.
The ESD protection circuit also includes a resistor 24 between the input pad 10 and the internal circuitry 22 to be protected. The purpose of the resistor is to better ensure that the first and second transistors 12 and 14 are the lower impedance paths for discharging most of an ESD charge before reaching the thin gate third transistor 20. That is, the resistor 24 functions to protect the third transistors from high voltages which potentially cause permanent damage. However, the resistor introduces an RC delay in the input path to the internal circuitry 22. This delay imposes a limitation to high speed circuitry.
Yet another limitation of the ESD protection circuit of FIG. 1 involves high voltage applications. If the internal circuitry 22 includes non-volatile high speed devices such as one or more PLD, EPROM, FPGA or flash device, an ESD protection circuit must be capable of withstanding high voltages under d.c. operating conditions. For example, a programming signal may require a 20 V input at the pad 10. While the metal field effect transistors 12 and 14 are typically not susceptible to damage under these high voltage conditions, the thin gate third transistor may breakdown and cause a permanent short to ground.
An object of the present invention is to provide a circuit which achieves protection for electrostatic discharge without introducing limitations to either high voltage or high speed circuit operations.